Key to Low Supply Voltage: Transition Region of Oxide Semiconductor Transistors

Abstract

We study the voltage transition region (TR) from sub- to above-threshold of field-effect transistors (FETs) and characterize its width (VTR) which informs how much the supply voltage (VDD) can be reduced. The TR is significant in amorphous oxide semiconductor field-effect transistors (OSFETs) because the shallow traps in amorphous OS channels lead to large VTR . We introduce a VTR extraction scheme and identify four main sources of shallow traps (ST) in amorphous OSFETs. We design experiments to individually evaluate their impact on VTR and successfully devise four OSFET process/design knobs to minimize V TR. Our analysis is then extended to other prominent FETs in the literature, with crystalline channel FETs showing VTR<80mV, in contrast to amorphous OSFETs with VTR ranging from 160 mV to as high as 1.1 V, highlighting that VTR in amorphous OSFETs is a critical challenge that must be addressed.