Orthogonal VT Tuning for Oxide Semiconductor 2T Gain Cell Enabled by Interface Dipole Engineering

Abstract

We demonstrate interface engineering (eng.) of the gate dielectric as an independent knob to tune the threshold voltage (VT) of Oxide Semiconductor (OS) FETs for twotransistor (2T) gain-cell memories (GC). By leveraging Interface Dipole (ID) eng. for Indium-Tungsten-Oxide (IWO) FETs, we achieve a ∼450−500mV VT increase compared to the standard HfO2 (STD), maintaining this ΔVT from 8°C to cryogenic temperatures. ID engineered (ID engd.) GCs exhibit good reliability, showing a ~60 mV shift under worst-case DC positive-bias stress (PBS) at 85°C. This approach is demonstrated across other OS such as Indium-Oxide, Indium-Tin-Oxide, and Indium-Gallium-Zinc-Oxide and at short channel lengths (sub-100 nm). Finally, simulations indicate that ID VT tuning reduces GC refresh energy by ∼50,000× compared to STD, enabling energy-efficient GC.