Multi-VT in Oxide-Semiconductor Transistors Leveraging Sub-1-nm Dipoles for Low-Refresh Energy Gain Cell Memory

Abstract

We demonstrate that inserting an ultrathin (<1 nm) Al₂O₃ layer between an oxide-semiconductor (OS) channel and a high-κ gate dielectric creates an interface dipole that shifts the threshold voltage (V_T) of OS transistors. The interface dipole (ID) engineering process by Al₂O₃ layer integration raises V_T of 2% W-doped indium tungsten oxide (IWO) FETs by ~450 mV relative to a reference HfO₂ stack, enabling normally-off operation with negligible degradation in mobility or sub-threshold swing. The V_T shift remains stable from 85°C down to cryogenic temperatures. Under a worst-case +2 V positive bias stress at 85°C, ID engineered OSFETs exhibit a ~60 mV shift versus ~300 mV for the baseline device. The technique is effective across multiple OS channels (In₂O₃, ITO, IGZO) and gate lengths down to ~50 nm. Simulations calibrated to the measured devices show that the leakage reduction afforded by ID engineering decreases refresh energy of two transistor gain-cell (2T-GC) arrays by ~5×10⁴×, establishing interface dipole engineering as a low thermal budget knob for energy-efficient, high density GC memories.