Optimization is Key to High-Temperature Reliability in Oxide-Semiconductor FETs

Abstract

Oxide semiconductor field-effect transistors (OSFETs) with back-end-of-line compatibility and ultralow leakage have potential for high-density on-chip memories. Two-transistor gain-cell (GC) memories, where write and read transistors share a storage node, are attractive for global buffers in TPU-like systolic arrays and KV cache for large language models [1]–[3]. However, repeated read/write operations and standby state cause prolonged bias stress and device self-heating, resulting in progressive negative threshold voltage shifts (ΔVT). In this work we investigate the positive bias stress (PBS) stability from below room temperature (−15∘C) to high temperatures (85∘C) in atomic-layer-deposited Indium Tungsten Oxide (IWO) FETs with standard HfO2 and optimized gate dielectric (Dstd ) and (Dopt ), respectively. We define a “critical temperature” (Tcrit )- the point at which hydrogen release mechanism overtake deep-electron trapping and show that Dopt with Tcrit near 85∘C exhibits significantly lower ΔVT at 85∘C compared to Dstd. Further analysis reveals that very high Tcrit values (e.g., 125∘C) increase temperature sensitivity highlighting the importance of designing OSFETs around an optimal Tcrit for reliable, high throughput data buffering.